1. Field of the Invention
The present invention generally relates to methods and systems for checking spacing of wiring in a semiconductor structure and more particularly to a method and system for checking the spacing of wiring within a single net.
2. Description of the Related Art
Conventional design rules require wires of the same net within a semiconductor structure to be spaced a specified minimum distance apart. A net can be defined as a set of logically connected shapes (typically terminals on logic gates) which are electrically connected when modeled physically. Older designs satisfied the minimum spacing requirements fairly easily through simplified grid designs which automatically guaranteed that minimum spacing design rules were met. However, with advancing technologies wider wires are more prevalent. Such wide wires have larger spacing requirements than the older narrower wires. Therefore, a simple gridded solution is no longer effective with today""s current wide wires.
Minimum spacing violations were conventionally recognized during the shapes processing performed by Design Rules Check (DRC). Design Rules Check is an expensive and time consuming process which is usually run after the final physical design layout is complete. Further, correcting minimum spacing violations after the final physical design layout is complete is also a difficult and expensive process. Therefore, there is a conventional need for a system and method for checking a given net for spacing violations which is fast, inexpensive and can be performed before the final physical design layout is complete.
It is, therefore, an object of the present invention to provide a structure and method for testing spacing of wiring in a circuit comprising forming a plurality of conductor rectangles representative of conductors of the circuit, forming minimum spacing rectangles around the conductor rectangles (the minimum spacing rectangles being larger than respective ones of the conductor rectangles), identifying a possible error rectangle when a first conductor rectangle of the conductor rectangles occupies a portion of a minimum spacing rectangle of a second conductor rectangle of the conductor rectangles, checking whether the possible error rectangle is a true error, and reporting the true errors.
The checking process comprises classifying the possible error rectangle as a possible diagonal error rectangle or a possible non-diagonal error rectangle, determining that the possible diagonal error rectangle is not a true error when at least two adjacent sides of the possible diagonal error rectangle which connect the first conductor and the second conductor are covered by a third conductor of the conductors, and determining that the possible non-diagonal error rectangle is not a true error when the possible non-diagonal error rectangle is completely covered by the third conductor.
The process of forming minimum spacing rectangles comprises forming the minimum spacing rectangles to have sides which are a minimum spacing design constraint distance from sides of respective ones of the conductor rectangles.
The conductors are preferably within a single net. If the circuit comprises a plurality of nets the process further includes checking for shorts between different ones of the nets.
The invention can also include dividing the possible error rectangle into at least two possible error rectangle if the possible error rectangle is partially covered by a third conductor of the conductors.
The invention is superior to conventional systems because the invention allows same net spacing errors to be recognized during physical design prior to Design Rules Check. The software supporting the invention performs orders of magnitude faster than the Design Rules Check solution. As such, the invention dramatically decreases the turn-around time of physical design, providing a fast solution which is available prior to final layout release.